1. Field of the Invention
The present invention relates to a circuit for compression of moving images, such as television images. It more specifically relates to the estimation of motions of portions of images, a portion of a current image being compared with its environment in the preceding image.
2. Discussion of the Related Art
A circuit of this type is used for coding the images so that they can be transmitted, in the context of a video image transmission, while minimizing the amount of information to be transmitted. The compression performed by the circuit consists, among others, in performing an estimation of the motion between portions of two successive images. This motion estimation enables to code, and thus to transmit, for portions of a current image, only motion vectors and distortion information associated with these portions.
The images, for example, coming from a video camera, are cut into image portions, called "macroblocks". These macroblocks generally correspond to a cutting up of the image into squares, each square having a dimension of 16.times.16 pixels. An image is stored sequentially, line by line, in a video memory, and the pixels so stored are extracted from this video memory by sets of pixels corresponding to square portions of the image. These sets of pixels, or macroblocks, are stored in a cache memory, to be used by a computer for, among others, determining the motion vector of the considered macroblock.
To perform the motion estimation of a macroblock, the computer is provided not only with the pixels of the considered macroblock of the current image, but also with pixels surrounding the corresponding macroblock in the preceding image. The computer sequentially processes each macroblock of the current image, by using, at least partially, the pixels of neighboring macroblocks in the preceding image which constitute a set of reference values, called the "reference window". In practice, a first cache memory contains the current macroblock and a second cache memory contains a larger reference window. This reference window includes, in addition to the pixels of the considered macroblock in the preceding image, at least part of the pixels of the macroblocks of the preceding image which are sequentially neighbor thereto in all directions.
FIG. 1 schematically shows an example of motion estimation device to which the present invention applies.
This device communicates by means of buses 1, 2, with a processor that controls the moving image compression circuit and with a processor that controls access to a video memory containing the data to be processed. The motion estimator includes a first finished state machine 3 (TOP CONTROL) managing the operation of the motion estimator and, in particular, the writing of the data into cache memories 4 (CW_RAM) and 5 (SW_RAM) for containing, respectively, the current macroblock to be processed and the reference window associated therewith. State machine 3 includes a link 6 to bus 1 and transfers the data, that it receives via a link 7 to bus 2, to controllers 8, 9 (CTRL) of memories 4, 5, via links 10, 11, on which the data, the write addresses and the control signals altogether transit. An example of addressing of a cache memory of a moving image compression circuit is described in patent application Ser. No. 94/05339, the content of which is incorporated herein by reference.
The estimation of the motion of a macroblock consists of determining the motion vector of this macroblock with respect to a macroblock of the preceding image and the distortion between the two macroblocks, that is, the cumulated difference between the pixels of the two macroblocks. The motion vector is determined by searching, in the reference window, the macroblock which exhibits a minimum distortion.
The vector of motion of a current macroblock with respect to the position of this macroblock in the preceding image is determined by examining the cumulated distortion of all the pixels in this current macroblock with respect to the pixels of macroblocks extracted from the reference window in all the positions likely to be taken by the current macroblock in this reference window. For this purpose, the motion estimator includes a unit 12 (DIST_OPE) of operators organized in systolic architecture which calculate, in parallel for a given motion in one direction, the distortion of the current macroblock with respect to all motions in the other direction. Unit 12 includes two data inputs 13 and 14 connected to the data outputs of memories 4, 5, for receiving, for each calculation cycle, a new pixel from each of the memories. Unit 12 includes as many outputs 15 as it includes operators. These outputs are connected to a unit 16 (MIN_OPE) of determination of the minimum distortion to determine the motion vector of the current macroblock. An output 17 of unit 16 issues this motion vector and the corresponding distortion to a set of registers 18 (REG), communicating over a link 19 with state machine 3. The set of registers 18 is meant to store the operation parameters supplied by the control processor of the moving image compression circuit and the results of the operations performed. Units 12 and 16 communicate, via links 20 and 21, with a second finished state machine 22 (OPE_CONTROL) for, in particular, organizing the reading of the data from memories 4 and 5. Read control signals of memories 4 and 5 and information relative to the state of progress of the operational process are issued by outputs 23, 24 of state machine 22 to transcoders 25, 26 (TRC) respectively associated with memories 4, 5. Transcoders 25, 26 determine, based on state signals issued by machine 22 and coming from counters (not shown), the read addresses of memories 4, 5.
The motion estimator shown in FIG. 1 is likely to perform a hierarchic motion estimation, that is, an estimation including several phases of different level for each macroblock. A first phase corresponds, for example, to searching the minimum distortion based on a macroblock and a reference window decimated by a factor two and then determining a motion vector to within two pixels. A second phase consists of determining the motion vector to within half a pixel based on a macroblock and a reference window reconstituted by linear interpolation. The use of a hierarchic (or telescopic) process of motion estimation is well known in the art. For clarity, it will be spoken of a macroblock, be it a portion of a basic, decimated, or interpolation-obtained image. It should only be noted that the data present in memories 4 and 5 must be coherent with one another.
The different phases are performed by means of the same motion estimator, and state machine 3 communicates parameters characteristic of each phase to the different components of the estimator. For this purpose, state machine 3 uses links 27, 28, 29, with state machine 22, transcoder 25 and transcoder 26 as well as links 19, 20, and 21 previously described. It should be noted that all components of the motion estimator, including the state machine, the operator units and the transcoders are wired, that is, are implemented in hardware form, as opposed to a software form.
The use of a hierarchic search process is linked, in particular, with the size of the reference window and with the image transmission rate. Indeed, the larger the reference window, the more necessary it is to perform a great number of operations for a given image transmission rate. For example, in an H263 standard applied to videophony, the macroblocks contain 16.times.16 pixels and the search is to be performed with a motion of plus or minus 16 pixels in all directions. Further, this standard provides an accuracy which can be as much as to within half a pixel by linear interpolation. The application of a search in the entire reference window in a single phase as has been previously done for the application to an H261 standard is not applicable since it would lead to using too large a number of operators. Standard H261 applies to the processing of images in the so-called "QCIF" format transmitted at a rate of 15 images per second, where each image is formed of 99 macroblocks of 16.times.16 pixels. Standard H263 provides the processing of images in the so-called "CIF" format at a rate of 30 images per second, where each image includes 396 macroblocks of 16.times.16 pixels. The application of the methods used for standard H261 would lead to providing around 480 parallel operators.
Further, if the application of a hierarchic search process enables respecting the time constraints for the determination of the motion vectors of the entire macroblocks, standard H263 also provides an operating mode in which the accuracy is increased by determining the motion of four separate blocks in each macroblock. It is then no longer possible to maintain the time constraints of the images at the CIF format with a unit 12 including 16 parallel operators.